{
  "design": {
    "design_info": {
      "boundary_crc": "0xFB80029CA111838A",
      "device": "xc7k480tffg1156-2",
      "name": "Top",
      "synth_flow_mode": "None",
      "tool_version": "2019.1",
      "validated": "true"
    },
    "design_tree": {
      "xdma_0": "",
      "axi_bram_ctrl_0": "",
      "axi_bram_ctrl_0_bram": "",
      "axi_smc": "",
      "axi_gpio_0": "",
      "vio_0": "",
      "util_vector_logic_0": "",
      "util_ds_buf_0": "",
      "mig_7series_0": "",
      "rst_mig_7series_0_133M": "",
      "rst_mig_7series_0_133M_1": "",
      "axi_smc1": ""
    },
    "interface_ports": {
      "pcie_7x_mgt": {
        "mode": "Master",
        "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0"
      },
      "PCIe_CLK": {
        "mode": "Slave",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000"
          }
        }
      },
      "C0_DDR3_0": {
        "mode": "Master",
        "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
        "parameters": {
          "AXI_ARBITRATION_SCHEME": {
            "value": "TDM",
            "value_src": "default"
          },
          "BURST_LENGTH": {
            "value": "8",
            "value_src": "default"
          },
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "CAS_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CAS_WRITE_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CS_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_MASK_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_WIDTH": {
            "value": "8",
            "value_src": "default"
          },
          "MEMORY_TYPE": {
            "value": "COMPONENTS",
            "value_src": "default"
          },
          "MEM_ADDR_MAP": {
            "value": "ROW_COLUMN_BANK",
            "value_src": "default"
          },
          "SLOT": {
            "value": "Single",
            "value_src": "default"
          },
          "TIMEPERIOD_PS": {
            "value": "1250",
            "value_src": "default"
          }
        }
      },
      "C1_DDR3_0": {
        "mode": "Master",
        "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
        "parameters": {
          "AXI_ARBITRATION_SCHEME": {
            "value": "TDM",
            "value_src": "default"
          },
          "BURST_LENGTH": {
            "value": "8",
            "value_src": "default"
          },
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "CAS_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CAS_WRITE_LATENCY": {
            "value": "11",
            "value_src": "default"
          },
          "CS_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_MASK_ENABLED": {
            "value": "true",
            "value_src": "default"
          },
          "DATA_WIDTH": {
            "value": "8",
            "value_src": "default"
          },
          "MEMORY_TYPE": {
            "value": "COMPONENTS",
            "value_src": "default"
          },
          "MEM_ADDR_MAP": {
            "value": "ROW_COLUMN_BANK",
            "value_src": "default"
          },
          "SLOT": {
            "value": "Single",
            "value_src": "default"
          },
          "TIMEPERIOD_PS": {
            "value": "1250",
            "value_src": "default"
          }
        }
      },
      "C0_SYS_CLK_0": {
        "mode": "Slave",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          }
        }
      },
      "C1_SYS_CLK_0": {
        "mode": "Slave",
        "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0",
        "parameters": {
          "CAN_DEBUG": {
            "value": "false",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "100000000",
            "value_src": "default"
          }
        }
      }
    },
    "ports": {
      "clk_50": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "CLK_DOMAIN": {
            "value": "Top_clk_50",
            "value_src": "default"
          },
          "FREQ_HZ": {
            "value": "50000000"
          },
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "PHASE": {
            "value": "0.000",
            "value_src": "default"
          }
        }
      },
      "LED": {
        "direction": "O",
        "left": "2",
        "right": "0"
      },
      "PCIe_RST_n": {
        "type": "rst",
        "direction": "I",
        "parameters": {
          "INSERT_VIP": {
            "value": "0",
            "value_src": "default"
          },
          "POLARITY": {
            "value": "ACTIVE_LOW"
          }
        }
      }
    },
    "components": {
      "xdma_0": {
        "vlnv": "xilinx.com:ip:xdma:4.1",
        "xci_name": "Top_xdma_0_0",
        "parameters": {
          "PF0_DEVICE_ID_mqdma": {
            "value": "9024"
          },
          "PF2_DEVICE_ID_mqdma": {
            "value": "9024"
          },
          "PF3_DEVICE_ID_mqdma": {
            "value": "9024"
          },
          "axi_data_width": {
            "value": "128_bit"
          },
          "axilite_master_en": {
            "value": "true"
          },
          "axilite_master_size": {
            "value": "4"
          },
          "axisten_freq": {
            "value": "125"
          },
          "cfg_mgmt_if": {
            "value": "false"
          },
          "pf0_Use_Class_Code_Lookup_Assistant": {
            "value": "true"
          },
          "pf0_base_class_menu": {
            "value": "Memory_controller"
          },
          "pf0_device_id": {
            "value": "7024"
          },
          "pf0_interrupt_pin": {
            "value": "NONE"
          },
          "pf0_link_status_slot_clock_config": {
            "value": "false"
          },
          "pf0_msix_cap_pba_bir": {
            "value": "BAR_1"
          },
          "pf0_msix_cap_pba_offset": {
            "value": "00008FE0"
          },
          "pf0_msix_cap_table_bir": {
            "value": "BAR_1"
          },
          "pf0_msix_cap_table_offset": {
            "value": "00008000"
          },
          "pf0_msix_cap_table_size": {
            "value": "01F"
          },
          "pf0_msix_enabled": {
            "value": "true"
          },
          "pf0_sub_class_interface_menu": {
            "value": "Other_memory_controller"
          },
          "pl_link_cap_max_link_speed": {
            "value": "5.0_GT/s"
          },
          "pl_link_cap_max_link_width": {
            "value": "X4"
          },
          "plltype": {
            "value": "QPLL1"
          },
          "xdma_axi_intf_mm": {
            "value": "AXI_Memory_Mapped"
          },
          "xdma_pcie_64bit_en": {
            "value": "false"
          },
          "xdma_rnum_chnl": {
            "value": "1"
          },
          "xdma_wnum_chnl": {
            "value": "1"
          }
        }
      },
      "axi_bram_ctrl_0": {
        "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1",
        "xci_name": "Top_axi_bram_ctrl_0_0",
        "parameters": {
          "SINGLE_PORT_BRAM": {
            "value": "1"
          }
        }
      },
      "axi_bram_ctrl_0_bram": {
        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
        "xci_name": "Top_axi_bram_ctrl_0_bram_0"
      },
      "axi_smc": {
        "vlnv": "xilinx.com:ip:smartconnect:1.0",
        "xci_name": "Top_axi_smc_2",
        "parameters": {
          "NUM_CLKS": {
            "value": "3"
          },
          "NUM_MI": {
            "value": "2"
          },
          "NUM_SI": {
            "value": "1"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "bridges": [
              "M00_AXI",
              "M01_AXI"
            ]
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        }
      },
      "axi_gpio_0": {
        "vlnv": "xilinx.com:ip:axi_gpio:2.0",
        "xci_name": "Top_axi_gpio_0_0",
        "parameters": {
          "C_ALL_INPUTS": {
            "value": "0"
          },
          "C_ALL_OUTPUTS": {
            "value": "1"
          },
          "C_GPIO_WIDTH": {
            "value": "3"
          }
        }
      },
      "vio_0": {
        "vlnv": "xilinx.com:ip:vio:3.0",
        "xci_name": "Top_vio_0_1",
        "parameters": {
          "C_NUM_PROBE_IN": {
            "value": "2"
          },
          "C_PROBE_OUT0_WIDTH": {
            "value": "3"
          }
        }
      },
      "util_vector_logic_0": {
        "vlnv": "xilinx.com:ip:util_vector_logic:2.0",
        "xci_name": "Top_util_vector_logic_0_0",
        "parameters": {
          "C_OPERATION": {
            "value": "or"
          },
          "C_SIZE": {
            "value": "3"
          }
        }
      },
      "util_ds_buf_0": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.1",
        "xci_name": "Top_util_ds_buf_0_0",
        "parameters": {
          "C_BUF_TYPE": {
            "value": "IBUFDSGTE"
          }
        }
      },
      "mig_7series_0": {
        "vlnv": "xilinx.com:ip:mig_7series:4.2",
        "xci_name": "Top_mig_7series_0_0",
        "parameters": {
          "BOARD_MIG_PARAM": {
            "value": "Custom"
          },
          "MIG_DONT_TOUCH_PARAM": {
            "value": "Custom"
          },
          "RESET_BOARD_INTERFACE": {
            "value": "Custom"
          },
          "XML_INPUT_FILE": {
            "value": "mig_a.prj"
          }
        }
      },
      "rst_mig_7series_0_133M": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "Top_rst_mig_7series_0_133M_0"
      },
      "rst_mig_7series_0_133M_1": {
        "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
        "xci_name": "Top_rst_mig_7series_0_133M_1_0"
      },
      "axi_smc1": {
        "vlnv": "xilinx.com:ip:smartconnect:1.0",
        "xci_name": "Top_axi_smc_3",
        "parameters": {
          "NUM_CLKS": {
            "value": "3"
          },
          "NUM_MI": {
            "value": "4"
          },
          "NUM_SI": {
            "value": "1"
          }
        },
        "interface_ports": {
          "S00_AXI": {
            "mode": "Slave",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
            "bridges": [
              "M00_AXI",
              "M01_AXI",
              "M02_AXI",
              "M03_AXI"
            ]
          },
          "M00_AXI": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M01_AXI": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M02_AXI": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          },
          "M03_AXI": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:aximm_rtl:1.0"
          }
        }
      }
    },
    "interface_nets": {
      "pcie_clk_1": {
        "interface_ports": [
          "PCIe_CLK",
          "util_ds_buf_0/CLK_IN_D"
        ]
      },
      "xdma_0_M_AXI_LITE": {
        "interface_ports": [
          "xdma_0/M_AXI_LITE",
          "axi_smc1/S00_AXI"
        ]
      },
      "axi_smc1_M02_AXI": {
        "interface_ports": [
          "axi_smc1/M02_AXI",
          "mig_7series_0/S0_AXI_CTRL"
        ]
      },
      "mig_7series_0_C0_DDR3": {
        "interface_ports": [
          "C0_DDR3_0",
          "mig_7series_0/C0_DDR3"
        ]
      },
      "C1_SYS_CLK_0_1": {
        "interface_ports": [
          "C1_SYS_CLK_0",
          "mig_7series_0/C1_SYS_CLK"
        ]
      },
      "C0_SYS_CLK_0_1": {
        "interface_ports": [
          "C0_SYS_CLK_0",
          "mig_7series_0/C0_SYS_CLK"
        ]
      },
      "axi_smc1_M03_AXI": {
        "interface_ports": [
          "axi_smc1/M03_AXI",
          "mig_7series_0/S1_AXI_CTRL"
        ]
      },
      "axi_smc1_M01_AXI": {
        "interface_ports": [
          "axi_smc1/M01_AXI",
          "axi_gpio_0/S_AXI"
        ]
      },
      "mig_7series_0_C1_DDR3": {
        "interface_ports": [
          "C1_DDR3_0",
          "mig_7series_0/C1_DDR3"
        ]
      },
      "xdma_0_M_AXI": {
        "interface_ports": [
          "xdma_0/M_AXI",
          "axi_smc/S00_AXI"
        ]
      },
      "axi_smc_M01_AXI": {
        "interface_ports": [
          "axi_smc/M01_AXI",
          "mig_7series_0/S1_AXI"
        ]
      },
      "axi_smc1_M00_AXI": {
        "interface_ports": [
          "axi_smc1/M00_AXI",
          "axi_bram_ctrl_0/S_AXI"
        ]
      },
      "axi_bram_ctrl_0_BRAM_PORTA": {
        "interface_ports": [
          "axi_bram_ctrl_0_bram/BRAM_PORTA",
          "axi_bram_ctrl_0/BRAM_PORTA"
        ]
      },
      "xdma_0_pcie_mgt": {
        "interface_ports": [
          "pcie_7x_mgt",
          "xdma_0/pcie_mgt"
        ]
      },
      "axi_smc_M00_AXI": {
        "interface_ports": [
          "axi_smc/M00_AXI",
          "mig_7series_0/S0_AXI"
        ]
      }
    },
    "nets": {
      "xdma_0_axi_aclk": {
        "ports": [
          "xdma_0/axi_aclk",
          "axi_bram_ctrl_0/s_axi_aclk",
          "axi_smc/aclk",
          "axi_gpio_0/s_axi_aclk",
          "axi_smc1/aclk"
        ]
      },
      "xdma_0_axi_aresetn": {
        "ports": [
          "xdma_0/axi_aresetn",
          "axi_bram_ctrl_0/s_axi_aresetn",
          "axi_smc/aresetn",
          "axi_gpio_0/s_axi_aresetn",
          "mig_7series_0/sys_rst",
          "axi_smc1/aresetn"
        ]
      },
      "xdma_0_user_lnk_up": {
        "ports": [
          "xdma_0/user_lnk_up",
          "vio_0/probe_in0"
        ]
      },
      "vio_0_probe_out0": {
        "ports": [
          "vio_0/probe_out0",
          "util_vector_logic_0/Op1"
        ]
      },
      "axi_gpio_0_gpio_io_o": {
        "ports": [
          "axi_gpio_0/gpio_io_o",
          "util_vector_logic_0/Op2"
        ]
      },
      "util_vector_logic_0_Res": {
        "ports": [
          "util_vector_logic_0/Res",
          "LED"
        ]
      },
      "clk_50_1": {
        "ports": [
          "clk_50",
          "vio_0/clk"
        ]
      },
      "util_ds_buf_0_IBUF_OUT": {
        "ports": [
          "util_ds_buf_0/IBUF_OUT",
          "xdma_0/sys_clk"
        ]
      },
      "PCIe_RST_n_1": {
        "ports": [
          "PCIe_RST_n",
          "vio_0/probe_in1",
          "xdma_0/sys_rst_n"
        ]
      },
      "mig_7series_0_c0_ui_clk": {
        "ports": [
          "mig_7series_0/c0_ui_clk",
          "axi_smc/aclk1",
          "rst_mig_7series_0_133M/slowest_sync_clk",
          "axi_smc1/aclk1"
        ]
      },
      "mig_7series_0_c0_mmcm_locked": {
        "ports": [
          "mig_7series_0/c0_mmcm_locked",
          "rst_mig_7series_0_133M/dcm_locked"
        ]
      },
      "mig_7series_0_c0_ui_clk_sync_rst": {
        "ports": [
          "mig_7series_0/c0_ui_clk_sync_rst",
          "rst_mig_7series_0_133M/ext_reset_in"
        ]
      },
      "rst_mig_7series_0_133M_peripheral_aresetn": {
        "ports": [
          "rst_mig_7series_0_133M/peripheral_aresetn",
          "mig_7series_0/c0_aresetn"
        ]
      },
      "mig_7series_0_c1_ui_clk": {
        "ports": [
          "mig_7series_0/c1_ui_clk",
          "axi_smc/aclk2",
          "rst_mig_7series_0_133M_1/slowest_sync_clk",
          "axi_smc1/aclk2"
        ]
      },
      "mig_7series_0_c1_mmcm_locked": {
        "ports": [
          "mig_7series_0/c1_mmcm_locked",
          "rst_mig_7series_0_133M_1/dcm_locked"
        ]
      },
      "mig_7series_0_c1_ui_clk_sync_rst": {
        "ports": [
          "mig_7series_0/c1_ui_clk_sync_rst",
          "rst_mig_7series_0_133M_1/ext_reset_in"
        ]
      },
      "rst_mig_7series_0_133M_1_peripheral_aresetn": {
        "ports": [
          "rst_mig_7series_0_133M_1/peripheral_aresetn",
          "mig_7series_0/c1_aresetn"
        ]
      }
    },
    "addressing": {
      "/xdma_0": {
        "address_spaces": {
          "M_AXI": {
            "range": "16E",
            "width": "32",
            "segments": {
              "SEG_mig_7series_0_c0_memaddr": {
                "address_block": "/mig_7series_0/c0_memmap/c0_memaddr",
                "offset": "0x0000000000000000",
                "range": "2G"
              },
              "SEG_mig_7series_0_c1_memaddr": {
                "address_block": "/mig_7series_0/c1_memmap/c1_memaddr",
                "offset": "0x0000000080000000",
                "range": "2G"
              }
            }
          },
          "M_AXI_LITE": {
            "range": "4G",
            "width": "32",
            "segments": {
              "SEG_axi_bram_ctrl_0_Mem0": {
                "address_block": "/axi_bram_ctrl_0/S_AXI/Mem0",
                "offset": "0x00000000",
                "range": "256K"
              },
              "SEG_axi_gpio_0_Reg": {
                "address_block": "/axi_gpio_0/S_AXI/Reg",
                "offset": "0x00040000",
                "range": "4K"
              },
              "SEG_mig_7series_0_c0_s_axi_ctrl_memaddr": {
                "address_block": "/mig_7series_0/c0_s_axi_ctrl_memmap/c0_s_axi_ctrl_memaddr",
                "offset": "0x00100000",
                "range": "1M"
              },
              "SEG_mig_7series_0_c1_s_axi_ctrl_memaddr": {
                "address_block": "/mig_7series_0/c1_s_axi_ctrl_memmap/c1_s_axi_ctrl_memaddr",
                "offset": "0x00200000",
                "range": "1M"
              }
            }
          }
        }
      }
    }
  }
}