verilog xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_clock.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_eq.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_drp.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_rate.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_reset.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_sync.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gtp_pipe_rate.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gtp_pipe_drp.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gtp_pipe_reset.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_user.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pipe_wrapper.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_qpll_drp.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_qpll_reset.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_qpll_wrapper.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_rxeq_scan.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_top.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_core_top.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_rx_null_gen.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_rx_pipeline.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_rx.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_top.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_tx_pipeline.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_tx_thrtl_ctl.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_axi_basic_tx.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_7x.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_bram_7x.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_bram_top_7x.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_brams_7x.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_pipe_lane.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_pipe_misc.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie_pipe_pipeline.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gt_top.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gt_common.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gtp_cpllpd_ovrd.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gtx_cpllpd_ovrd.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gt_rx_valid_filter_7x.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_gt_wrapper.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/source/Top_xdma_0_0_pcie2_ip_pcie2_top.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_0/sim/Top_xdma_0_0_pcie2_ip.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_1/sim/xdma_v4_1_3_blk_mem_64_reg_be.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_2/sim/xdma_v4_1_3_blk_mem_64_noreg_be.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_3/sim/pcie2_fifo_generator_dma_cpl.v" \
"../../../bd/Top/ip/Top_xdma_0_0/ip_4/sim/pcie2_fifo_generator_tgt_brdg.v" \

sv xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_dma_cpl.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_dma_req.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_rx_destraddler.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_rx_demux.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_tgt_cpl.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_tgt_req.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_tx_mux.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_axi_stream_intf.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_cfg_sideband.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_pcie2_to_pcie3_wrapper.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_dma_bram_wrap.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_dma_bram_wrap_1024.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/xdma_v4_1/hdl/verilog/Top_xdma_0_0_core_top.sv" \
"../../../bd/Top/ip/Top_xdma_0_0/sim/Top_xdma_0_0.sv" \

verilog xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_axi_bram_ctrl_0_bram_0/sim/Top_axi_bram_ctrl_0_bram_0.v" \
"../../../bd/Top/sim/Top.v" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/sim/bd_15c4.v" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_0/sim/bd_15c4_one_0.v" \

sv xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_5/sim/bd_15c4_arsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_6/sim/bd_15c4_rsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_7/sim/bd_15c4_awsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_8/sim/bd_15c4_wsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_9/sim/bd_15c4_bsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_10/sim/bd_15c4_s00mmu_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_11/sim/bd_15c4_s00tr_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_12/sim/bd_15c4_s00sic_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_13/sim/bd_15c4_s00a2s_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_14/sim/bd_15c4_sarn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_15/sim/bd_15c4_srn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_16/sim/bd_15c4_sawn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_17/sim/bd_15c4_swn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_18/sim/bd_15c4_sbn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_19/sim/bd_15c4_m00s2a_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_20/sim/bd_15c4_m00arn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_21/sim/bd_15c4_m00rn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_22/sim/bd_15c4_m00awn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_23/sim/bd_15c4_m00wn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_24/sim/bd_15c4_m00bn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_25/sim/bd_15c4_m00e_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_26/sim/bd_15c4_m01s2a_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_27/sim/bd_15c4_m01arn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_28/sim/bd_15c4_m01rn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_29/sim/bd_15c4_m01awn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_30/sim/bd_15c4_m01wn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_31/sim/bd_15c4_m01bn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_2/bd_0/ip/ip_32/sim/bd_15c4_m01e_0.sv" \

verilog xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_axi_smc_2/sim/Top_axi_smc_2.v" \
"../../../bd/Top/ip/Top_vio_0_1/sim/Top_vio_0_1.v" \
"../../../bd/Top/ip/Top_util_vector_logic_0_0/sim/Top_util_vector_logic_0_0.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_top.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_top.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_col_mach.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_common.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_mc.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_rank_common.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_state.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_2_arb_select.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_fsm.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_r_upsizer.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_a_upsizer.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_addr_decode.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_simple_fifo.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_arbiter.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_and.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_ar_channel.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_and.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_command_fifo.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_or.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_read.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_upsizer.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_top.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_w_upsizer.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_comparator_sel_static.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_reg_bank.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_ctrl_write.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_2_ddr_carry_latch_or.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/Top_mig_7series_0_0_mig_sim.v" \
"../../../bd/Top/ip/Top_mig_7series_0_0/Top_mig_7series_0_0/user_design/rtl/Top_mig_7series_0_0.v" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/sim/bd_d505.v" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_0/sim/bd_d505_one_0.v" \

sv xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_5/sim/bd_d505_arsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_6/sim/bd_d505_rsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_7/sim/bd_d505_awsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_8/sim/bd_d505_wsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_9/sim/bd_d505_bsw_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_10/sim/bd_d505_s00mmu_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_11/sim/bd_d505_s00tr_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_12/sim/bd_d505_s00sic_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_13/sim/bd_d505_s00a2s_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_14/sim/bd_d505_sarn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_15/sim/bd_d505_srn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_16/sim/bd_d505_sawn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_17/sim/bd_d505_swn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_18/sim/bd_d505_sbn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_19/sim/bd_d505_m00s2a_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_20/sim/bd_d505_m00arn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_21/sim/bd_d505_m00rn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_22/sim/bd_d505_m00awn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_23/sim/bd_d505_m00wn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_24/sim/bd_d505_m00bn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_25/sim/bd_d505_m00e_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_26/sim/bd_d505_m01s2a_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_27/sim/bd_d505_m01arn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_28/sim/bd_d505_m01rn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_29/sim/bd_d505_m01awn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_30/sim/bd_d505_m01wn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_31/sim/bd_d505_m01bn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_32/sim/bd_d505_m01e_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_33/sim/bd_d505_m02s2a_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_34/sim/bd_d505_m02arn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_35/sim/bd_d505_m02rn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_36/sim/bd_d505_m02awn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_37/sim/bd_d505_m02wn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_38/sim/bd_d505_m02bn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_39/sim/bd_d505_m02e_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_40/sim/bd_d505_m03s2a_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_41/sim/bd_d505_m03arn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_42/sim/bd_d505_m03rn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_43/sim/bd_d505_m03awn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_44/sim/bd_d505_m03wn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_45/sim/bd_d505_m03bn_0.sv" \
"../../../bd/Top/ip/Top_axi_smc_3/bd_0/ip/ip_46/sim/bd_d505_m03e_0.sv" \

verilog xil_defaultlib --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/90ef/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1ddd/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/b2d0/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/1b7e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/122e/hdl/verilog" --include "../../../../XDMA_480T_n.srcs/sources_1/bd/Top/ipshared/9ba5/hdl" \
"../../../bd/Top/ip/Top_axi_smc_3/sim/Top_axi_smc_3.v" \

verilog xil_defaultlib "glbl.v"

nosort
