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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor             : Xilinx
// \   \   \/     Version            : 4.2
//  \   \         Application        : MIG
//  /   /         Filename           : Top_mig_7series_0_0.v
// /___/   /\     Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \   \  /  \    Date Created       : Wed Feb 01 2012
//  \___\/\___\
//
// Device           : 7 Series
// Design Name      : DDR3 SDRAM
// Purpose          :
//   Wrapper module for the user design top level file. This module can be 
//   instantiated in the system and interconnect as shown in example design 
//   (example_top module).
// Revision History :
//*****************************************************************************
//`define SKIP_CALIB
`timescale 1ps/1ps

module Top_mig_7series_0_0 (
  // Inouts
  inout [71:0]       c0_ddr3_dq,
  inout [8:0]        c0_ddr3_dqs_n,
  inout [8:0]        c0_ddr3_dqs_p,
  // Outputs
  output [14:0]     c0_ddr3_addr,
  output [2:0]        c0_ddr3_ba,
  output            c0_ddr3_ras_n,
  output            c0_ddr3_cas_n,
  output            c0_ddr3_we_n,
  output            c0_ddr3_reset_n,
  output [0:0]       c0_ddr3_ck_p,
  output [0:0]       c0_ddr3_ck_n,
  output [0:0]       c0_ddr3_cke,
  output [0:0]        c0_ddr3_cs_n,
  output [0:0]       c0_ddr3_odt,
  // Inputs
  // Differential system clocks
  input             c0_sys_clk_p,
  input             c0_sys_clk_n,
  // user interface signals
  output            c0_ui_clk,
  output            c0_ui_clk_sync_rst,
  output            c0_mmcm_locked,
  output [7:0]         c0_app_ecc_multiple_err,
  output [7:0]         c0_app_ecc_single_err,
  input         c0_aresetn,
  output            c0_app_sr_active,
  output            c0_app_ref_ack,
  output            c0_app_zq_ack,
  // Slave Interface Write Address Ports
  input [3:0]           c0_s_axi_awid,
  input [30:0]         c0_s_axi_awaddr,
  input [7:0]           c0_s_axi_awlen,
  input [2:0]           c0_s_axi_awsize,
  input [1:0]           c0_s_axi_awburst,
  input [0:0]           c0_s_axi_awlock,
  input [3:0]           c0_s_axi_awcache,
  input [2:0]           c0_s_axi_awprot,
  input [3:0]           c0_s_axi_awqos,
  input         c0_s_axi_awvalid,
  output            c0_s_axi_awready,
  // Slave Interface Write Data Ports
  input [511:0]         c0_s_axi_wdata,
  input [63:0]         c0_s_axi_wstrb,
  input         c0_s_axi_wlast,
  input         c0_s_axi_wvalid,
  output            c0_s_axi_wready,
  // Slave Interface Write Response Ports
  input         c0_s_axi_bready,
  output [3:0]          c0_s_axi_bid,
  output [1:0]          c0_s_axi_bresp,
  output            c0_s_axi_bvalid,
  // Slave Interface Read Address Ports
  input [3:0]           c0_s_axi_arid,
  input [30:0]         c0_s_axi_araddr,
  input [7:0]           c0_s_axi_arlen,
  input [2:0]           c0_s_axi_arsize,
  input [1:0]           c0_s_axi_arburst,
  input [0:0]           c0_s_axi_arlock,
  input [3:0]           c0_s_axi_arcache,
  input [2:0]           c0_s_axi_arprot,
  input [3:0]           c0_s_axi_arqos,
  input         c0_s_axi_arvalid,
  output            c0_s_axi_arready,
  // Slave Interface Read Data Ports
  input         c0_s_axi_rready,
  output [3:0]          c0_s_axi_rid,
  output [511:0]            c0_s_axi_rdata,
  output [1:0]          c0_s_axi_rresp,
  output            c0_s_axi_rlast,
  output            c0_s_axi_rvalid,
  // AXI CTRL port
  input         c0_s_axi_ctrl_awvalid,
  output            c0_s_axi_ctrl_awready,
  input [31:0]          c0_s_axi_ctrl_awaddr,
  // Slave Interface Write Data Ports
  input         c0_s_axi_ctrl_wvalid,
  output            c0_s_axi_ctrl_wready,
  input [31:0]          c0_s_axi_ctrl_wdata,
  // Slave Interface Write Response Ports
  output            c0_s_axi_ctrl_bvalid,
  input         c0_s_axi_ctrl_bready,
  output [1:0]          c0_s_axi_ctrl_bresp,
  // Slave Interface Read Address Ports
  input         c0_s_axi_ctrl_arvalid,
  output            c0_s_axi_ctrl_arready,
  input [31:0]          c0_s_axi_ctrl_araddr,
  // Slave Interface Read Data Ports
  output            c0_s_axi_ctrl_rvalid,
  input         c0_s_axi_ctrl_rready,
  output [31:0]         c0_s_axi_ctrl_rdata,
  output [1:0]          c0_s_axi_ctrl_rresp,
  // Interrupt output
  output            c0_interrupt,
  output            c0_init_calib_complete,
  output [11:0]                                c0_device_temp,
`ifdef SKIP_CALIB
   output                                      c0_calib_tap_req,
   input                                       c0_calib_tap_load,
   input [6:0]                                 c0_calib_tap_addr,
   input [7:0]                                 c0_calib_tap_val,
   input                                       c0_calib_tap_load_done,
`endif
    // Inouts
  inout [71:0]       c1_ddr3_dq,
  inout [8:0]        c1_ddr3_dqs_n,
  inout [8:0]        c1_ddr3_dqs_p,
  // Outputs
  output [14:0]     c1_ddr3_addr,
  output [2:0]        c1_ddr3_ba,
  output            c1_ddr3_ras_n,
  output            c1_ddr3_cas_n,
  output            c1_ddr3_we_n,
  output            c1_ddr3_reset_n,
  output [0:0]       c1_ddr3_ck_p,
  output [0:0]       c1_ddr3_ck_n,
  output [0:0]       c1_ddr3_cke,
  output [0:0]        c1_ddr3_cs_n,
  output [0:0]       c1_ddr3_odt,
  // Inputs
  // Differential system clocks
  input             c1_sys_clk_p,
  input             c1_sys_clk_n,
  // user interface signals
  output            c1_ui_clk,
  output            c1_ui_clk_sync_rst,
  output            c1_mmcm_locked,
  output [7:0]         c1_app_ecc_multiple_err,
  output [7:0]         c1_app_ecc_single_err,
  input         c1_aresetn,
  output            c1_app_sr_active,
  output            c1_app_ref_ack,
  output            c1_app_zq_ack,
  // Slave Interface Write Address Ports
  input [3:0]           c1_s_axi_awid,
  input [30:0]         c1_s_axi_awaddr,
  input [7:0]           c1_s_axi_awlen,
  input [2:0]           c1_s_axi_awsize,
  input [1:0]           c1_s_axi_awburst,
  input [0:0]           c1_s_axi_awlock,
  input [3:0]           c1_s_axi_awcache,
  input [2:0]           c1_s_axi_awprot,
  input [3:0]           c1_s_axi_awqos,
  input         c1_s_axi_awvalid,
  output            c1_s_axi_awready,
  // Slave Interface Write Data Ports
  input [511:0]         c1_s_axi_wdata,
  input [63:0]         c1_s_axi_wstrb,
  input         c1_s_axi_wlast,
  input         c1_s_axi_wvalid,
  output            c1_s_axi_wready,
  // Slave Interface Write Response Ports
  input         c1_s_axi_bready,
  output [3:0]          c1_s_axi_bid,
  output [1:0]          c1_s_axi_bresp,
  output            c1_s_axi_bvalid,
  // Slave Interface Read Address Ports
  input [3:0]           c1_s_axi_arid,
  input [30:0]         c1_s_axi_araddr,
  input [7:0]           c1_s_axi_arlen,
  input [2:0]           c1_s_axi_arsize,
  input [1:0]           c1_s_axi_arburst,
  input [0:0]           c1_s_axi_arlock,
  input [3:0]           c1_s_axi_arcache,
  input [2:0]           c1_s_axi_arprot,
  input [3:0]           c1_s_axi_arqos,
  input         c1_s_axi_arvalid,
  output            c1_s_axi_arready,
  // Slave Interface Read Data Ports
  input         c1_s_axi_rready,
  output [3:0]          c1_s_axi_rid,
  output [511:0]            c1_s_axi_rdata,
  output [1:0]          c1_s_axi_rresp,
  output            c1_s_axi_rlast,
  output            c1_s_axi_rvalid,
  // AXI CTRL port
  input         c1_s_axi_ctrl_awvalid,
  output            c1_s_axi_ctrl_awready,
  input [31:0]          c1_s_axi_ctrl_awaddr,
  // Slave Interface Write Data Ports
  input         c1_s_axi_ctrl_wvalid,
  output            c1_s_axi_ctrl_wready,
  input [31:0]          c1_s_axi_ctrl_wdata,
  // Slave Interface Write Response Ports
  output            c1_s_axi_ctrl_bvalid,
  input         c1_s_axi_ctrl_bready,
  output [1:0]          c1_s_axi_ctrl_bresp,
  // Slave Interface Read Address Ports
  input         c1_s_axi_ctrl_arvalid,
  output            c1_s_axi_ctrl_arready,
  input [31:0]          c1_s_axi_ctrl_araddr,
  // Slave Interface Read Data Ports
  output            c1_s_axi_ctrl_rvalid,
  input         c1_s_axi_ctrl_rready,
  output [31:0]         c1_s_axi_ctrl_rdata,
  output [1:0]          c1_s_axi_ctrl_rresp,
  // Interrupt output
  output            c1_interrupt,
  output            c1_init_calib_complete,
  output [11:0]                                c1_device_temp,
`ifdef SKIP_CALIB
   output                                      c1_calib_tap_req,
   input                                       c1_calib_tap_load,
   input [6:0]                                 c1_calib_tap_addr,
   input [7:0]                                 c1_calib_tap_val,
   input                                       c1_calib_tap_load_done,
`endif
  
  input			sys_rst
  );

// Start of IP top instance
  Top_mig_7series_0_0_mig u_Top_mig_7series_0_0_mig (

    // Memory interface ports
    .c0_ddr3_addr                      (c0_ddr3_addr),
    .c0_ddr3_ba                        (c0_ddr3_ba),
    .c0_ddr3_cas_n                     (c0_ddr3_cas_n),
    .c0_ddr3_ck_n                      (c0_ddr3_ck_n),
    .c0_ddr3_ck_p                      (c0_ddr3_ck_p),
    .c0_ddr3_cke                       (c0_ddr3_cke),
    .c0_ddr3_ras_n                     (c0_ddr3_ras_n),
    .c0_ddr3_reset_n                   (c0_ddr3_reset_n),
    .c0_ddr3_we_n                      (c0_ddr3_we_n),
    .c0_ddr3_dq                        (c0_ddr3_dq),
    .c0_ddr3_dqs_n                     (c0_ddr3_dqs_n),
    .c0_ddr3_dqs_p                     (c0_ddr3_dqs_p),
    .c0_init_calib_complete            (c0_init_calib_complete),
      
    .c0_ddr3_cs_n                      (c0_ddr3_cs_n),
    .c0_ddr3_odt                       (c0_ddr3_odt),
    // Application interface ports
    .c0_ui_clk                         (c0_ui_clk),
    .c0_ui_clk_sync_rst                (c0_ui_clk_sync_rst),
    .c0_mmcm_locked                    (c0_mmcm_locked),
    .c0_aresetn                        (c0_aresetn),
    .c0_app_sr_active                  (c0_app_sr_active),
    .c0_app_ref_ack                    (c0_app_ref_ack),
    .c0_app_zq_ack                     (c0_app_zq_ack),
    // Slave Interface Write Address Ports
    .c0_s_axi_awid                     (c0_s_axi_awid),
    .c0_s_axi_awaddr                   (c0_s_axi_awaddr),
    .c0_s_axi_awlen                    (c0_s_axi_awlen),
    .c0_s_axi_awsize                   (c0_s_axi_awsize),
    .c0_s_axi_awburst                  (c0_s_axi_awburst),
    .c0_s_axi_awlock                   (c0_s_axi_awlock),
    .c0_s_axi_awcache                  (c0_s_axi_awcache),
    .c0_s_axi_awprot                   (c0_s_axi_awprot),
    .c0_s_axi_awqos                    (c0_s_axi_awqos),
    .c0_s_axi_awvalid                  (c0_s_axi_awvalid),
    .c0_s_axi_awready                  (c0_s_axi_awready),
    // Slave Interface Write Data Ports
    .c0_s_axi_wdata                    (c0_s_axi_wdata),
    .c0_s_axi_wstrb                    (c0_s_axi_wstrb),
    .c0_s_axi_wlast                    (c0_s_axi_wlast),
    .c0_s_axi_wvalid                   (c0_s_axi_wvalid),
    .c0_s_axi_wready                   (c0_s_axi_wready),
    // Slave Interface Write Response Ports
    .c0_s_axi_bid                      (c0_s_axi_bid),
    .c0_s_axi_bresp                    (c0_s_axi_bresp),
    .c0_s_axi_bvalid                   (c0_s_axi_bvalid),
    .c0_s_axi_bready                   (c0_s_axi_bready),
    // Slave Interface Read Address Ports
    .c0_s_axi_arid                     (c0_s_axi_arid),
    .c0_s_axi_araddr                   (c0_s_axi_araddr),
    .c0_s_axi_arlen                    (c0_s_axi_arlen),
    .c0_s_axi_arsize                   (c0_s_axi_arsize),
    .c0_s_axi_arburst                  (c0_s_axi_arburst),
    .c0_s_axi_arlock                   (c0_s_axi_arlock),
    .c0_s_axi_arcache                  (c0_s_axi_arcache),
    .c0_s_axi_arprot                   (c0_s_axi_arprot),
    .c0_s_axi_arqos                    (c0_s_axi_arqos),
    .c0_s_axi_arvalid                  (c0_s_axi_arvalid),
    .c0_s_axi_arready                  (c0_s_axi_arready),
    // Slave Interface Read Data Ports
    .c0_s_axi_rid                      (c0_s_axi_rid),
    .c0_s_axi_rdata                    (c0_s_axi_rdata),
    .c0_s_axi_rresp                    (c0_s_axi_rresp),
    .c0_s_axi_rlast                    (c0_s_axi_rlast),
    .c0_s_axi_rvalid                   (c0_s_axi_rvalid),
    .c0_s_axi_rready                   (c0_s_axi_rready),
    // AXI CTRL port
    .c0_s_axi_ctrl_awvalid             (c0_s_axi_ctrl_awvalid),
    .c0_s_axi_ctrl_awready             (c0_s_axi_ctrl_awready),
    .c0_s_axi_ctrl_awaddr              (c0_s_axi_ctrl_awaddr),
    // Slave Interface Write Data Ports
    .c0_s_axi_ctrl_wvalid              (c0_s_axi_ctrl_wvalid),
    .c0_s_axi_ctrl_wready              (c0_s_axi_ctrl_wready),
    .c0_s_axi_ctrl_wdata               (c0_s_axi_ctrl_wdata),
    // Slave Interface Write Response Ports
    .c0_s_axi_ctrl_bvalid              (c0_s_axi_ctrl_bvalid),
    .c0_s_axi_ctrl_bready              (c0_s_axi_ctrl_bready),
    .c0_s_axi_ctrl_bresp               (c0_s_axi_ctrl_bresp),
    // Slave Interface Read Address Ports
    .c0_s_axi_ctrl_arvalid             (c0_s_axi_ctrl_arvalid),
    .c0_s_axi_ctrl_arready             (c0_s_axi_ctrl_arready),
    .c0_s_axi_ctrl_araddr              (c0_s_axi_ctrl_araddr),
    // Slave Interface Read Data Ports
    .c0_s_axi_ctrl_rvalid              (c0_s_axi_ctrl_rvalid),
    .c0_s_axi_ctrl_rready              (c0_s_axi_ctrl_rready),
    .c0_s_axi_ctrl_rdata               (c0_s_axi_ctrl_rdata),
    .c0_s_axi_ctrl_rresp               (c0_s_axi_ctrl_rresp),
    // Interrupt output
    .c0_interrupt                      (c0_interrupt),
    .c0_app_ecc_multiple_err           (c0_app_ecc_multiple_err),
    .c0_app_ecc_single_err             (c0_app_ecc_single_err),
    // System Clock Ports
    .c0_sys_clk_p                       (c0_sys_clk_p),
    .c0_sys_clk_n                       (c0_sys_clk_n),
       .c0_device_temp            (c0_device_temp),
       `ifdef SKIP_CALIB
       .c0_calib_tap_req                    (c0_calib_tap_req),
       .c0_calib_tap_load                   (c0_calib_tap_load),
       .c0_calib_tap_addr                   (c0_calib_tap_addr),
       .c0_calib_tap_val                    (c0_calib_tap_val),
       .c0_calib_tap_load_done              (c0_calib_tap_load_done),
       `endif
    // Memory interface ports
    .c1_ddr3_addr                      (c1_ddr3_addr),
    .c1_ddr3_ba                        (c1_ddr3_ba),
    .c1_ddr3_cas_n                     (c1_ddr3_cas_n),
    .c1_ddr3_ck_n                      (c1_ddr3_ck_n),
    .c1_ddr3_ck_p                      (c1_ddr3_ck_p),
    .c1_ddr3_cke                       (c1_ddr3_cke),
    .c1_ddr3_ras_n                     (c1_ddr3_ras_n),
    .c1_ddr3_reset_n                   (c1_ddr3_reset_n),
    .c1_ddr3_we_n                      (c1_ddr3_we_n),
    .c1_ddr3_dq                        (c1_ddr3_dq),
    .c1_ddr3_dqs_n                     (c1_ddr3_dqs_n),
    .c1_ddr3_dqs_p                     (c1_ddr3_dqs_p),
    .c1_init_calib_complete            (c1_init_calib_complete),
      
    .c1_ddr3_cs_n                      (c1_ddr3_cs_n),
    .c1_ddr3_odt                       (c1_ddr3_odt),
    // Application interface ports
    .c1_ui_clk                         (c1_ui_clk),
    .c1_ui_clk_sync_rst                (c1_ui_clk_sync_rst),
    .c1_mmcm_locked                    (c1_mmcm_locked),
    .c1_aresetn                        (c1_aresetn),
    .c1_app_sr_active                  (c1_app_sr_active),
    .c1_app_ref_ack                    (c1_app_ref_ack),
    .c1_app_zq_ack                     (c1_app_zq_ack),
    // Slave Interface Write Address Ports
    .c1_s_axi_awid                     (c1_s_axi_awid),
    .c1_s_axi_awaddr                   (c1_s_axi_awaddr),
    .c1_s_axi_awlen                    (c1_s_axi_awlen),
    .c1_s_axi_awsize                   (c1_s_axi_awsize),
    .c1_s_axi_awburst                  (c1_s_axi_awburst),
    .c1_s_axi_awlock                   (c1_s_axi_awlock),
    .c1_s_axi_awcache                  (c1_s_axi_awcache),
    .c1_s_axi_awprot                   (c1_s_axi_awprot),
    .c1_s_axi_awqos                    (c1_s_axi_awqos),
    .c1_s_axi_awvalid                  (c1_s_axi_awvalid),
    .c1_s_axi_awready                  (c1_s_axi_awready),
    // Slave Interface Write Data Ports
    .c1_s_axi_wdata                    (c1_s_axi_wdata),
    .c1_s_axi_wstrb                    (c1_s_axi_wstrb),
    .c1_s_axi_wlast                    (c1_s_axi_wlast),
    .c1_s_axi_wvalid                   (c1_s_axi_wvalid),
    .c1_s_axi_wready                   (c1_s_axi_wready),
    // Slave Interface Write Response Ports
    .c1_s_axi_bid                      (c1_s_axi_bid),
    .c1_s_axi_bresp                    (c1_s_axi_bresp),
    .c1_s_axi_bvalid                   (c1_s_axi_bvalid),
    .c1_s_axi_bready                   (c1_s_axi_bready),
    // Slave Interface Read Address Ports
    .c1_s_axi_arid                     (c1_s_axi_arid),
    .c1_s_axi_araddr                   (c1_s_axi_araddr),
    .c1_s_axi_arlen                    (c1_s_axi_arlen),
    .c1_s_axi_arsize                   (c1_s_axi_arsize),
    .c1_s_axi_arburst                  (c1_s_axi_arburst),
    .c1_s_axi_arlock                   (c1_s_axi_arlock),
    .c1_s_axi_arcache                  (c1_s_axi_arcache),
    .c1_s_axi_arprot                   (c1_s_axi_arprot),
    .c1_s_axi_arqos                    (c1_s_axi_arqos),
    .c1_s_axi_arvalid                  (c1_s_axi_arvalid),
    .c1_s_axi_arready                  (c1_s_axi_arready),
    // Slave Interface Read Data Ports
    .c1_s_axi_rid                      (c1_s_axi_rid),
    .c1_s_axi_rdata                    (c1_s_axi_rdata),
    .c1_s_axi_rresp                    (c1_s_axi_rresp),
    .c1_s_axi_rlast                    (c1_s_axi_rlast),
    .c1_s_axi_rvalid                   (c1_s_axi_rvalid),
    .c1_s_axi_rready                   (c1_s_axi_rready),
    // AXI CTRL port
    .c1_s_axi_ctrl_awvalid             (c1_s_axi_ctrl_awvalid),
    .c1_s_axi_ctrl_awready             (c1_s_axi_ctrl_awready),
    .c1_s_axi_ctrl_awaddr              (c1_s_axi_ctrl_awaddr),
    // Slave Interface Write Data Ports
    .c1_s_axi_ctrl_wvalid              (c1_s_axi_ctrl_wvalid),
    .c1_s_axi_ctrl_wready              (c1_s_axi_ctrl_wready),
    .c1_s_axi_ctrl_wdata               (c1_s_axi_ctrl_wdata),
    // Slave Interface Write Response Ports
    .c1_s_axi_ctrl_bvalid              (c1_s_axi_ctrl_bvalid),
    .c1_s_axi_ctrl_bready              (c1_s_axi_ctrl_bready),
    .c1_s_axi_ctrl_bresp               (c1_s_axi_ctrl_bresp),
    // Slave Interface Read Address Ports
    .c1_s_axi_ctrl_arvalid             (c1_s_axi_ctrl_arvalid),
    .c1_s_axi_ctrl_arready             (c1_s_axi_ctrl_arready),
    .c1_s_axi_ctrl_araddr              (c1_s_axi_ctrl_araddr),
    // Slave Interface Read Data Ports
    .c1_s_axi_ctrl_rvalid              (c1_s_axi_ctrl_rvalid),
    .c1_s_axi_ctrl_rready              (c1_s_axi_ctrl_rready),
    .c1_s_axi_ctrl_rdata               (c1_s_axi_ctrl_rdata),
    .c1_s_axi_ctrl_rresp               (c1_s_axi_ctrl_rresp),
    // Interrupt output
    .c1_interrupt                      (c1_interrupt),
    .c1_app_ecc_multiple_err           (c1_app_ecc_multiple_err),
    .c1_app_ecc_single_err             (c1_app_ecc_single_err),
    // System Clock Ports
    .c1_sys_clk_p                       (c1_sys_clk_p),
    .c1_sys_clk_n                       (c1_sys_clk_n),
       .c1_device_temp            (c1_device_temp),
       `ifdef SKIP_CALIB
       .c1_calib_tap_req                    (c1_calib_tap_req),
       .c1_calib_tap_load                   (c1_calib_tap_load),
       .c1_calib_tap_addr                   (c1_calib_tap_addr),
       .c1_calib_tap_val                    (c1_calib_tap_val),
       .c1_calib_tap_load_done              (c1_calib_tap_load_done),
       `endif
    .sys_rst                        (sys_rst)
    );
// End of IP top instance

endmodule


