//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
//
// Project    : The Xilinx PCI Express DMA 
// File       : Top_xdma_0_0_dma_bram_wrap_1024.sv
// Version    : 4.1
//-----------------------------------------------------------------------------

`ifndef DMA_BRAM_WRAP_1024_SV
`define DMA_BRAM_WRAP_1024_SV

`include "xdma_axi4mm_axi_bridge.vh"
`include "dma_defines.vh"
`include "dma_defines.svh"

module xdma_v4_1_3_dma_bram_wrap_1024
#(
  parameter DATA_WIDTH = 256,
  parameter AXI4MM_ULTRA = 0,
  parameter ECC_ENABLE	= 0,
  parameter OUTPUT_REG = 0
  )
(
 input clkin,
 input [DATA_WIDTH-1:0]   DataIn,
 input [DATA_WIDTH/8-1:0] ParityIn,
 input [DATA_WIDTH/8-1:0] wrEn,
 input rdEn,
 input [9:0] AddrIn,
 input [9:0] AddrOut,
 output [DATA_WIDTH-1:0] DataOut,
 output			 DbeOut,
 output [DATA_WIDTH/8-1:0] ParityOut
 );


localparam	MEM_CNT		= (DATA_WIDTH / 64)+((DATA_WIDTH%64) != 0);
   
wire [DATA_WIDTH/64-1:0] dbiterr_wire;
assign			 DbeOut = (ECC_ENABLE) ? |dbiterr_wire : 1'b0;
genvar 		    memcnt;
generate
	for(memcnt=0;memcnt<MEM_CNT;memcnt=memcnt+1) 
	begin
		if (OUTPUT_REG == 0) 
				if (ECC_ENABLE == 0)
	      			xdma_v4_1_3_blk_mem_64_noreg_be_1024 u_buffermem(
					     .clka(clkin),
					     .wea(wrEn[memcnt*64/8+:8]),
					     .ena(1'b1),
					     .addra(AddrIn),
					     .dina({ParityIn[(memcnt*8)+7],DataIn[(memcnt*64+56)+:8],
					     	    ParityIn[(memcnt*8)+6],DataIn[(memcnt*64+48)+:8],
					     	    ParityIn[(memcnt*8)+5],DataIn[(memcnt*64+40)+:8],
					     	    ParityIn[(memcnt*8)+4],DataIn[(memcnt*64+32)+:8],
					     	    ParityIn[(memcnt*8)+3],DataIn[(memcnt*64+24)+:8],
					     	    ParityIn[(memcnt*8)+2],DataIn[(memcnt*64+16)+:8],
					     	    ParityIn[(memcnt*8)+1],DataIn[(memcnt*64+8 )+:8],
					     	    ParityIn[(memcnt*8)+0],DataIn[(memcnt*64+0)+:8]}),
					     .clkb(clkin),
					     .enb (rdEn),
					     .addrb(AddrOut),
					     .doutb({ParityOut[(memcnt*8)+7],DataOut[(memcnt*64+56)+:8],
					     	    ParityOut[(memcnt*8)+6],DataOut[(memcnt*64+48)+:8],
					     	    ParityOut[(memcnt*8)+5],DataOut[(memcnt*64+40)+:8],
					     	    ParityOut[(memcnt*8)+4],DataOut[(memcnt*64+32)+:8],
					     	    ParityOut[(memcnt*8)+3],DataOut[(memcnt*64+24)+:8],
					     	    ParityOut[(memcnt*8)+2],DataOut[(memcnt*64+16)+:8],
					     	    ParityOut[(memcnt*8)+1],DataOut[(memcnt*64+8)+:8],
					     	    ParityOut[(memcnt*8)+0],DataOut[(memcnt*64+0)+:8]})
					     );
				else 
	      			xdma_v4_1_3_blk_mem_64_noreg_ecc u_buffermem(
					.clka(clkin),
					.wea(wrEn[0]),
					.ena(1'b1),
					.addra(AddrIn),
					.dina(DataIn[(memcnt*64)+:64]),
					.clkb(clkin),
					.enb (rdEn),
					.addrb(AddrOut),
					.doutb(DataOut[(memcnt*64)+:64]),
					.dbiterr(dbiterr_wire[memcnt])
				);
	    	else
				if (ECC_ENABLE == 0)
	      			xdma_v4_1_3_blk_mem_64_reg_be u_buffermem(
					     .clka(clkin),
					     .ena(1'b1),
					     .wea(wrEn[memcnt*64/8+:8]),
					     .addra(AddrIn),
					     .dina({ParityIn[(memcnt*8)+7],DataIn[(memcnt*64+56)+:8],
					     	    ParityIn[(memcnt*8)+6],DataIn[(memcnt*64+48)+:8],
					     	    ParityIn[(memcnt*8)+5],DataIn[(memcnt*64+40)+:8],
					     	    ParityIn[(memcnt*8)+4],DataIn[(memcnt*64+32)+:8],
					     	    ParityIn[(memcnt*8)+3],DataIn[(memcnt*64+24)+:8],
					     	    ParityIn[(memcnt*8)+2],DataIn[(memcnt*64+16)+:8],
					     	    ParityIn[(memcnt*8)+1],DataIn[(memcnt*64+8)+:8],
					     	    ParityIn[(memcnt*8)+0],DataIn[(memcnt*64+0)+:8]}),
					     .clkb(clkin),
					     .enb (rdEn),
					     .addrb(AddrOut),
					     .doutb({ParityOut[(memcnt*8)+7],DataOut[(memcnt*64+56)+:8],
					     	    ParityOut[(memcnt*8)+6],DataOut[(memcnt*64+48)+:8],
					     	    ParityOut[(memcnt*8)+5],DataOut[(memcnt*64+40)+:8],
					     	    ParityOut[(memcnt*8)+4],DataOut[(memcnt*64+32)+:8],
					     	    ParityOut[(memcnt*8)+3],DataOut[(memcnt*64+24)+:8],
					     	    ParityOut[(memcnt*8)+2],DataOut[(memcnt*64+16)+:8],
					     	    ParityOut[(memcnt*8)+1],DataOut[(memcnt*64+8)+:8],
					     	    ParityOut[(memcnt*8)+0],DataOut[(memcnt*64+0)+:8]})
					     );
				else 
	      			xdma_v4_1_3_blk_mem_64_reg_ecc u_buffermem(
					.clka(clkin),
					.wea(wrEn[0]),
					.ena(1'b1),
					.addra(AddrIn),
					.dina(DataIn[(memcnt*64)+:64]),
					.clkb(clkin),
					.enb (rdEn),
					.addrb(AddrOut),
					.doutb(DataOut[(memcnt*64)+:64]),
					.dbiterr(dbiterr_wire[memcnt])
				);
	end
   endgenerate
   
endmodule

`endif

