//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
//Date        : Thu Sep  5 21:57:17 2024
//Host        : ai running 64-bit Ubuntu 22.04.2 LTS
//Command     : generate_target Top_wrapper.bd
//Design      : Top_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module Top_wrapper
   (C0_DDR3_0_addr,
    C0_DDR3_0_ba,
    C0_DDR3_0_cas_n,
    C0_DDR3_0_ck_n,
    C0_DDR3_0_ck_p,
    C0_DDR3_0_cke,
    C0_DDR3_0_cs_n,
    C0_DDR3_0_dq,
    C0_DDR3_0_dqs_n,
    C0_DDR3_0_dqs_p,
    C0_DDR3_0_odt,
    C0_DDR3_0_ras_n,
    C0_DDR3_0_reset_n,
    C0_DDR3_0_we_n,
    C0_SYS_CLK_0_clk_n,
    C0_SYS_CLK_0_clk_p,
    C1_DDR3_0_addr,
    C1_DDR3_0_ba,
    C1_DDR3_0_cas_n,
    C1_DDR3_0_ck_n,
    C1_DDR3_0_ck_p,
    C1_DDR3_0_cke,
    C1_DDR3_0_cs_n,
    C1_DDR3_0_dq,
    C1_DDR3_0_dqs_n,
    C1_DDR3_0_dqs_p,
    C1_DDR3_0_odt,
    C1_DDR3_0_ras_n,
    C1_DDR3_0_reset_n,
    C1_DDR3_0_we_n,
    C1_SYS_CLK_0_clk_n,
    C1_SYS_CLK_0_clk_p,
    LED,
    PCIe_CLK_clk_n,
    PCIe_CLK_clk_p,
    PCIe_RST_n,
    clk_50,
    pcie_7x_mgt_rxn,
    pcie_7x_mgt_rxp,
    pcie_7x_mgt_txn,
    pcie_7x_mgt_txp);
  output [14:0]C0_DDR3_0_addr;
  output [2:0]C0_DDR3_0_ba;
  output C0_DDR3_0_cas_n;
  output [0:0]C0_DDR3_0_ck_n;
  output [0:0]C0_DDR3_0_ck_p;
  output [0:0]C0_DDR3_0_cke;
  output [0:0]C0_DDR3_0_cs_n;
  inout [71:0]C0_DDR3_0_dq;
  inout [8:0]C0_DDR3_0_dqs_n;
  inout [8:0]C0_DDR3_0_dqs_p;
  output [0:0]C0_DDR3_0_odt;
  output C0_DDR3_0_ras_n;
  output C0_DDR3_0_reset_n;
  output C0_DDR3_0_we_n;
  input C0_SYS_CLK_0_clk_n;
  input C0_SYS_CLK_0_clk_p;
  output [14:0]C1_DDR3_0_addr;
  output [2:0]C1_DDR3_0_ba;
  output C1_DDR3_0_cas_n;
  output [0:0]C1_DDR3_0_ck_n;
  output [0:0]C1_DDR3_0_ck_p;
  output [0:0]C1_DDR3_0_cke;
  output [0:0]C1_DDR3_0_cs_n;
  inout [71:0]C1_DDR3_0_dq;
  inout [8:0]C1_DDR3_0_dqs_n;
  inout [8:0]C1_DDR3_0_dqs_p;
  output [0:0]C1_DDR3_0_odt;
  output C1_DDR3_0_ras_n;
  output C1_DDR3_0_reset_n;
  output C1_DDR3_0_we_n;
  input C1_SYS_CLK_0_clk_n;
  input C1_SYS_CLK_0_clk_p;
  output [2:0]LED;
  input [0:0]PCIe_CLK_clk_n;
  input [0:0]PCIe_CLK_clk_p;
  input PCIe_RST_n;
  input clk_50;
  input [3:0]pcie_7x_mgt_rxn;
  input [3:0]pcie_7x_mgt_rxp;
  output [3:0]pcie_7x_mgt_txn;
  output [3:0]pcie_7x_mgt_txp;

  wire [14:0]C0_DDR3_0_addr;
  wire [2:0]C0_DDR3_0_ba;
  wire C0_DDR3_0_cas_n;
  wire [0:0]C0_DDR3_0_ck_n;
  wire [0:0]C0_DDR3_0_ck_p;
  wire [0:0]C0_DDR3_0_cke;
  wire [0:0]C0_DDR3_0_cs_n;
  wire [71:0]C0_DDR3_0_dq;
  wire [8:0]C0_DDR3_0_dqs_n;
  wire [8:0]C0_DDR3_0_dqs_p;
  wire [0:0]C0_DDR3_0_odt;
  wire C0_DDR3_0_ras_n;
  wire C0_DDR3_0_reset_n;
  wire C0_DDR3_0_we_n;
  wire C0_SYS_CLK_0_clk_n;
  wire C0_SYS_CLK_0_clk_p;
  wire [14:0]C1_DDR3_0_addr;
  wire [2:0]C1_DDR3_0_ba;
  wire C1_DDR3_0_cas_n;
  wire [0:0]C1_DDR3_0_ck_n;
  wire [0:0]C1_DDR3_0_ck_p;
  wire [0:0]C1_DDR3_0_cke;
  wire [0:0]C1_DDR3_0_cs_n;
  wire [71:0]C1_DDR3_0_dq;
  wire [8:0]C1_DDR3_0_dqs_n;
  wire [8:0]C1_DDR3_0_dqs_p;
  wire [0:0]C1_DDR3_0_odt;
  wire C1_DDR3_0_ras_n;
  wire C1_DDR3_0_reset_n;
  wire C1_DDR3_0_we_n;
  wire C1_SYS_CLK_0_clk_n;
  wire C1_SYS_CLK_0_clk_p;
  wire [2:0]LED;
  wire [0:0]PCIe_CLK_clk_n;
  wire [0:0]PCIe_CLK_clk_p;
  wire PCIe_RST_n;
  wire clk_50;
  wire [3:0]pcie_7x_mgt_rxn;
  wire [3:0]pcie_7x_mgt_rxp;
  wire [3:0]pcie_7x_mgt_txn;
  wire [3:0]pcie_7x_mgt_txp;

  Top Top_i
       (.C0_DDR3_0_addr(C0_DDR3_0_addr),
        .C0_DDR3_0_ba(C0_DDR3_0_ba),
        .C0_DDR3_0_cas_n(C0_DDR3_0_cas_n),
        .C0_DDR3_0_ck_n(C0_DDR3_0_ck_n),
        .C0_DDR3_0_ck_p(C0_DDR3_0_ck_p),
        .C0_DDR3_0_cke(C0_DDR3_0_cke),
        .C0_DDR3_0_cs_n(C0_DDR3_0_cs_n),
        .C0_DDR3_0_dq(C0_DDR3_0_dq),
        .C0_DDR3_0_dqs_n(C0_DDR3_0_dqs_n),
        .C0_DDR3_0_dqs_p(C0_DDR3_0_dqs_p),
        .C0_DDR3_0_odt(C0_DDR3_0_odt),
        .C0_DDR3_0_ras_n(C0_DDR3_0_ras_n),
        .C0_DDR3_0_reset_n(C0_DDR3_0_reset_n),
        .C0_DDR3_0_we_n(C0_DDR3_0_we_n),
        .C0_SYS_CLK_0_clk_n(C0_SYS_CLK_0_clk_n),
        .C0_SYS_CLK_0_clk_p(C0_SYS_CLK_0_clk_p),
        .C1_DDR3_0_addr(C1_DDR3_0_addr),
        .C1_DDR3_0_ba(C1_DDR3_0_ba),
        .C1_DDR3_0_cas_n(C1_DDR3_0_cas_n),
        .C1_DDR3_0_ck_n(C1_DDR3_0_ck_n),
        .C1_DDR3_0_ck_p(C1_DDR3_0_ck_p),
        .C1_DDR3_0_cke(C1_DDR3_0_cke),
        .C1_DDR3_0_cs_n(C1_DDR3_0_cs_n),
        .C1_DDR3_0_dq(C1_DDR3_0_dq),
        .C1_DDR3_0_dqs_n(C1_DDR3_0_dqs_n),
        .C1_DDR3_0_dqs_p(C1_DDR3_0_dqs_p),
        .C1_DDR3_0_odt(C1_DDR3_0_odt),
        .C1_DDR3_0_ras_n(C1_DDR3_0_ras_n),
        .C1_DDR3_0_reset_n(C1_DDR3_0_reset_n),
        .C1_DDR3_0_we_n(C1_DDR3_0_we_n),
        .C1_SYS_CLK_0_clk_n(C1_SYS_CLK_0_clk_n),
        .C1_SYS_CLK_0_clk_p(C1_SYS_CLK_0_clk_p),
        .LED(LED),
        .PCIe_CLK_clk_n(PCIe_CLK_clk_n),
        .PCIe_CLK_clk_p(PCIe_CLK_clk_p),
        .PCIe_RST_n(PCIe_RST_n),
        .clk_50(clk_50),
        .pcie_7x_mgt_rxn(pcie_7x_mgt_rxn),
        .pcie_7x_mgt_rxp(pcie_7x_mgt_rxp),
        .pcie_7x_mgt_txn(pcie_7x_mgt_txn),
        .pcie_7x_mgt_txp(pcie_7x_mgt_txp));
endmodule
